Arrangement for energy conditioning

ABSTRACT

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

This application is a US national stage application of internationalapplication PCT/US02/21238, filed Jul. 2, 2001, now abandoned which is acontinuation-in-part of application Ser. No. 10/023,467, filed Dec. 17,2001, now abandoned which is a continuation-in-part of application Ser.No. 09/996,355, filed Nov. 29, 2001, now abandoned which is acontinuation-in-part of application Ser. No. 10/003,711, filed Nov. 15,2001, now abandoned which is a continuation-in-part of application Ser.No. 09/982,553, filed Oct. 17, 2001, and this application is acontinuation-in-part of application Ser. No. 10/115,159, filed Apr. 2,2002, now U.S. Pat. No. 6,894,884, which is a continuation-in-partapplication Ser. No. 09/845,680, filed Apr. 30, 2001, now issued as U.S.Pat. No. 6,580,595, which is a continuation-in-part of application Ser.No. 09/777,021 filed Feb. 5, 2001, now U.S. Pat. No. 6,687,108, which isa continuation-in-part of application Ser. No. 09/632,048, filed Aug. 3,2000, now U.S. Pat. No. 6,738,249, which is a continuation-in-part ofapplication Ser. No. 09/594,447, filed Jun. 15, 2000, now U.S. Pat. No.6,636,406, which is a continuation-in-part of application No.09/579,606, filed May 26, 2000, now issued as U.S. Pat. No. 6,373,673,which is a continuation-in-part of application Ser. No. 09/460,218,filed Dec. 13, 1999, now issued as U.S. Pat. No. 6,331,926, which is acontinuation of application Ser. No. 09/056,379, filed Apr. 7, 1998, nowissued as U.S. Pat. No. 6,018,448, which is a continuation-in-part ofapplication Ser. No. 09/008,769, filed Jan. 19, 1998, now issued as U.S.Pat. No. 6,097,581, which is a continuation-in-part of application Ser.No. 08/841,940, filed Apr. 8, 1997, now issued as U.S. Pat. No.5,909,350, and application Ser. No. 10/115,159 claims the benefit ofU.S. Provisional Application No. 60/280,819, filed Apr. 2, 2001, U.S.Provisional Application No. 60/302,429, filed Jul. 2, 2001, and U.S.Provisional Application No. 60/310,962, filed Aug. 8, 2001, andapplication Ser. No. 09/845,680 claims the benefit of priority of U.S.Provisional Application No. 60/200,327, filed Apr. 28, 2000, U.S.Provisional Application No. 60/215,314, filed Jun. 30, 2000, U.S.Provisional Application No. 60/225,497, filed Aug. 15, 2000, and U.S.Provisional Application No. 60/255,818, filed Dec. 15, 2000, andapplication Ser. No. 09/777,021 claims the benefit of priority of U.S.Provisional Application No. 60/180,101, filed Feb. 3, 2000, U.S.Provisional Application No. 60/185,320, filed Feb. 28, 2000, U.S.Provisional Application No. 60/191,196, filed Mar. 22, 2000, U.S.Provisional Application No. 60/200,327, filed Apr. 28, 2000, U.S.Provisional Application No. 60/203,863, filed May 12, 2000, U.S.Provisional Application No. 60/215,314, filed Jun. 30, 2000, U.S.Provisional Application No. 60/225,497, filed Aug. 15, 2000, U.S.Provisional Application No. 60/241,128, filed Oct. 17, 2000, U.S.Provisional Application No. 60/248,914, filed Nov. 15, 2000, U.S.Provisional Application No. 60/252,766, filed Nov. 22, 2000, U.S.Provisional Application No. 60/253,793, filed Nov. 29, 2000, and U.S.Provisional Application 60/255,818, filed Dec. 15, 2000, and applicationSer. No. 09/632,048, claims the benefit of U.S. Provisional ApplicationNo. 60/146,987, filed Aug. 3, 1999, U.S. Provisional Application No.60/165,035, filed Nov. 12, 1999, U.S. Provisional Application No.60/180,101, filed Feb. 3, 2000, U.S. Provisional Application No.60/185,320, filed Feb. 28, 2000, U.S. Provisional Application No.60/191,196, filed Mar. 22, 2000, U.S. Provisional Application No.60/200,327, filed Apr. 28, 2000, and U.S. Provisional Application No.60/203,863, filed May 12, 2000, and application Ser. No. 09/594,447,claims the benefit of priority of U.S. Provisional Application No.60/139,182, filed Jun. 15, 1999, U.S. Provisional Application No.60/146,987, filed Aug. 3, 1999, U.S. Provisional Application No.60/165,035, filed Nov. 12, 1999, U.S. Provisional Application No.60/180,101, filed Feb. 3, 2000, U.S. Provisional Application No.60/185,320, filed Feb. 28, 2000, U.S. Provisional Application No.60/191,196, filed Mar. 22, 2000, U.S. Provisional Application No.60/200,327, filed Apr. 28, 2000, and U.S. Provisional Application No.60/203,863, filed May 12, 2000, and application Ser. No. 09/579,606claims the benefit of U.S. Provisional Application No. 60/136,451, filedMay 28, 1999, U.S. Provisional Application No. 60/139,182, filed Jun.15, 1999, U.S. Provisional Application No. 60/146,987, filed Aug. 3,1999, U.S. Provisional Application No. 60/165,035, filed Nov. 12, 1999,U.S. Provisional Application No. 60/180,101, filed Feb. 3, 2000, U.S.Provisional Application No. 60/185,320, filed Feb. 28, 2000, U.S.Provisional Application No. 60/200,327, filed Apr. 28, 2000, and U.S.Provisional Application No. 60/203,863, filed May 12, 2000, andapplication Ser. No. 10/023,467 claims the benefit of U.S. ProvisionalApplication No. 60/255,818, filed Dec. 15, 2000, U.S. ProvisionalApplication No. 60/280,819, filed Apr. 2, 2001, U.S. ProvisionalApplication No. 60/302,429, filed Jul. 2, 2001, and U.S. ProvisionalApplication No. 60/310,962, filed Aug. 8, 2001, and application Ser. No.09/982,553 claims the benefit of U.S. Provisional Application No.60/241,128, filed Oct. 17, 2000, and application No. 09/996,355 claimsthe benefit of U.S. Provisional Application No. 60/253,793, filed Nov.29, 2000, U.S. Provisional Application No. 60/255,818, filed Dec. 15,2000, U.S. Provisional Application No. 60/280,819, filed Apr. 2, 2001,U.S. Provisional Application No. 60/302,429, filed Jul. 2, 2001, andU.S. Provisional Application No. 60/310,962, filed Aug. 8, 2001, andapplication Ser. No. 10/003,711 claims the benefit of U.S. ProvisionalApplication No. 60/248,914, filed Nov. 15, 2000, U.S. ProvisionalApplication No. 60/252,766, filed Nov. 22, 2000, U.S. ProvisionalApplication No. 60/253,793, filed Nov. 29, 2000, U.S. ProvisionalApplication No. 60/255,818, filed Dec. 15, 2000, U.S. ProvisionalApplication No. 60/280,819, filed Apr. 2, 2001, U.S. ProvisionalApplication No. 60/302,429, filed Jul. 2, 2001, and U.S. ProvisionalApplication No. 60/310,962, filed Aug. 8, 2001, and applicationPCT/US02/21238 claims the benefit under 35 U.S.C. 119(e) of U.S.Provisional Application No. 60/302,429, filed Jul. 2, 2001, U.S.Provisional Application No. 60/310,962, filed Aug. 8, 2001, and U.S.Provisional Application No. 60/388,388, filed Jun. 12, 2002.

TECHNICAL FIELD

In addition, this application claims the benefit of U.S. ProvisionalApplication No. 60/302,429, filed Jul. 2, 2001, U.S. ProvisionalApplication No. 60/310,962, filed Aug. 8, 2001, U.S. ProvisionalApplication No. 60/349,954, filed Jan. 8, 2002, and U.S. ProvisionalApplication No. (Not assigned), filed Jun. 12, 2002.

This application relates to balanced shielding arrangements that usecomplementary relative groupings of energy pathways, such as pathwaysfor various energy propagations for multiple energy conditioningfunctions. These shielding arrangements may be operable as discrete ornon-discrete embodiments that can sustain and condition electricallycomplementary energy confluences.

BACKGROUND

Today, as the density of electronics within applications increases,unwanted noise byproducts of the increased density may limit theperformance electronic circuitry. Consequently, the avoidance of theeffects of unwanted noise byproducts, such as by isolation orimmunization of circuits against the effects of the undesirable noise isan important consideration for circuit arrangements and circuit design.

Differential and common mode noise energy may be generated by, and maypropagate along or around, energy pathways, cables, circuit board tracksor traces, high-speed transmission lines, and/or bus line pathways.These energy conductors may act as, for example, an antenna thatradiates energy fields. This antenna-analogous performance mayexacerbate the noise problem in that, at higher frequencies, propagatingenergy utilizing prior art passive devices may experience increasedlevels of energy parasitic interference, such as various capacitiveand/or inductive parasitics.

These increases may be due, in part, to the combination of constraintsresulting from functionally or structurally limitations of prior artsolutions, coupled with the inherent manufacturing or design imbalancesand performance deficiencies of the prior art. These deficienciesinherently create, or induce, unwanted and unbalanced interferenceenergy that may couple into associated electrical circuitry, therebymaking at least partial shielding from these parasitics andelectromagnetic interference desirable. Consequently, for broadfrequency operating environments, solving these problems necessitates atleast a combination of simultaneous filtration, careful systems layouthaving various grounding or anti-noise arrangements, as well asextensive isolating in combination with at least partial electrostaticand electromagnetic shielding.

Thus, a need exists for a self-contained, energy-conditioningarrangement utilizing simplified energy pathway arrangements, which mayadditionally include other elements, amalgamated into a discreet ornon-discreet component, which may be utilized in almost any circuitapplication for providing effective, symmetrically balanced, andsustainable, simultaneous energy conditioning functions selected from atleast a decoupling function, transient suppression function, noisecancellation function, energy blocking function, and energy suppressionfunctions.

BRIEF DESCRIPTION OF THE DRAWINGS

Understanding of the present invention will be facilitated byconsideration of the following detailed description of the preferredembodiments of the present invention taken in conjunction with theaccompanying drawings, in which like numerals refer to like parts and inwhich:

FIG. 1 is a relative location compass operable for determining relativelocations of the various pathway extensions disclosed;

FIGS. 1A-1C show relative locations of the various pathway extensionsdisclosed according to an aspect of the present invention;

FIG. 2A shows a circuit schematic of the plan view of an embodiment of2B according to an aspect of the resent invention;

FIG. 2B is a plan view of an embodiment according to an aspect of thepresent invention;

FIG. 3A shows a circuit schematic of the plan view of an embodiment of3B according to an aspect of the present invention;

FIG. 3B is a plan view of an embodiment according to an aspect of thepresent invention;

FIG. 3C shows a plan view of a shield according to an aspect of thepresent invention;

FIG. 4A shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 4B shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 4C shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 4D shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 4E shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 4F shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 4G shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 4H shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 4I shows a relative plan view of an embodiment according to anaspect of the present invention;

FIG. 5A shows a stacked multiple, circuit network including groups ofpathways according to an aspect of the present invention;

FIG. 5B shows a stacked shield according to an aspect of the presentinvention;

FIG. 5C shows a relative plan view of a stacked multiple, non-sharedcircuit network having VIAs including groups of pathways according to anaspect of the present invention;

FIG. 6 shows a relative plan view of circuit arrangement variantaccording to an aspect of the present invention; and,

FIG. 7 shows a relative plan view of circuit arrangement variantaccording to an aspect of the present invention;

DETAILED DESCRIPTION

This application is a continuation-in-part of co-pending applicationSer. No. 10/023,467, filed Dec. 17, 2001, which is acontinuation-in-part of co-pending application Ser. No. 09/996,355,filed Nov. 29, 2001, which is a continuation-in-part of co-pendingapplication Ser. No. 10/003,711, filed Nov. 17, 2001, which is acontinuation-in-part of co-pending application Ser. No. 09/982,553,filed Oct. 17, 2001, each of which is incorporated by reference herein.

In addition, this application claims the benefit of U.S. ProvisionalApplication No. 60/302,429, filed Jul. 2, 2001, U.S. ProvisionalApplication No. 60/310,962, filed Aug. 8, 2001, U.S. ProvisionalApplication No. 60/349,954, filed Jan. 8, 2002, and U.S. ProvisionalApplication No. (Not assigned), filed Jun. 12, 2002, each of which isincorporated by reference herein.

It is to be understood that the figures and descriptions of the presentinvention have been simplified to illustrate elements that are relevantfor a clear understanding of the present invention, while eliminating,for the purpose of clarity, many other elements found in typical energyconditioning systems and methods. Those of ordinary skill in the artwill recognize that other elements and/or steps are desirable and/orrequired in implementing the present invention. However, because suchelements and steps are well known in the art, and because they do notfacilitate a better understanding of the present invention, a discussionof such elements and steps is not provided herein. The disclosure hereinis directed to all such variations and modifications to such elementsand methods known to those skilled in the art. Additionally, it will beapparent to those skilled in the art that terms used herein that mayinclude a whole, or a portion of a whole, such as “energy”, “system”,circuit, and the like, are contemplated to include both the portions ofthe whole, and the entire of the whole, as used, unless otherwise noted.

As used herein, an “energy pathway” or “pathway” may be at least one, ora number, of conductive materials, each one operable for sustainedpropagation of energy. Pathways may be conductive, thereby betterpropagating various electrical energies as compared to non-conductive orsemi-conductive materials directly or indirectly coupled to, or adjacentto, the pathways. An energy pathway may facilitate propagation of afirst energy by allowing for various energy conditioning functions, suchas conditioning functions arising due to any one or a number of aspects,such as, but not limited to, the shielding, the orientation and/or thepositioning of the energy pathways within the energy pathwayarrangement, which various arrangements having an orientation and/orpositioning thereby allow for interaction of the first energy withpropagating energies that are complementary to at least the firstenergy. An energy pathway may include an energy pathway portion, anentire energy pathway, a conductor, an energy conductor, an electrode,at least one process-created conductor, and/or a shield. A plurality ofenergy pathways may include a plurality of each device or elementdiscussed hereinabove with respect to energy pathway. Further, as usedgenerally herein, a conductor may include, for example, an individualconductive material portion, a conductive plane, a conductive pathway, apathway, an electrical wire, a via, an aperture, a conductive portionsuch as a resistive lead, a conductive material portion, or anelectrical plate, such as plates separated by at least one medium 801,for example.

A shield may include a shielding electrode, a shielding pathway portion,a shielded pathway, a shielded conductor, a shielded energy conductor, ashielded electrode, and/or at least one process-created shielded pathwayportion. A plurality of shields may include a plurality of the devicesdiscussed hereinabove with respect to a shield.

As used generally herein, a pathway may be complementary positioned, orcomplementary orientated, with respect to a main-body 80, 81, havingvarious pathway extensions, designated 79“X”, 812“X”, 811“X” and 99“X”.Main-bodies 80, 81 may be in three-dimensional physical relationshipsindividually, in pairs, groups, and/or pluralities as to distance,orientation, position, superposition, non-superposition, alignment,partial alignment, lapping, non-lapping, and partial lapping. Superposedmain-body pathway 80, may, for example include a pairing of physicallyopposing and oppositely orientated main-body pathways 80 that are anyone of, or any combination of, electrically null, electricallycomplementary, electrically differential, or electrically opposite.

A pathway arrangement may include at least a shield at least partiallyshielding at least one energy pathway, or a group of shields forming ashield structure that at least partially shielding, via a conductiveshielding, at least a conductively isolated pairing of at least twoenergy pathways, such as vias, apertures or complementary pairedpathways.

An exemplary embodiment may allow energy propagation on a conductivelyisolated pairing, such as complementary paired pathways, causing energypropagation on common shields, or at least one grouping of shields,serving an isolated circuit. This embodiment may allow a low inductancepathway to form among at least a single pair of isolated and separateparallel pathways serving at least one separate and distinct isolatedcircuit system. An exemplary embodiment may allow for the development ofat least a low inductance pathway for utilization of energy propagatingon at least one parallel pathway of at least two sets of isolated andseparate parallel pathways and the development along at least oneparallel pathway of at least one other low inductance pathway forutilization of energy propagating along at least one other separate anddistinct isolated circuit system.

An exemplary embodiment utilized as part of a circuit assembly may haveat least one pathway of relatively lower inductance, while otherpathways may be electrically coupled to an energy source or an energyload. A pathway of a second plurality of pathways may have a lowerimpedance operable for portions of energy to be taken away from eitherof the same at least one energy source or at least one energy load ofthe circuit assembly. This same pathway of low impedance may not beelectrically directly coupled to either the same at least one energysource or at least one energy load of the circuit assembly as the onepathway of lower inductance. A system may have both a pathway of leastinductance and a pathway of least impedance which are not the samepathway.

In contrast to capacitors found in the industry wherein an equivalentseries inductance (ESL) of a capacitor device is normally sizedependant, in the present invention the pathway of least impedance andthe pathway of least inductance for a circuit for energy conditioningmay be achieved independent of the physical size of the device. Theseaspects depend on a predetermined capacitance developed by apredetermined layers in the present invention.

Arranging the pathways allows the resistance of the conductive materialof the pathways to primarily determine the energy delivery, or relativeefficiency or effect between at least one source of energy and oneenergy utilizing load of an integrated circuit, for example. The ESL maybe a negligible factor, rather than a primary factor for deliveryoutcome or decoupling void of debilitating inductances.

In an illustrative pathway arrangement illustrated in FIGS. 1A, 1B, 1C,5A and 5B, wherein the various propagating energies may becomplementary, the pathway arrangement, upon placement into a circuitarrangement, may allow for energy propagation within or along certainenergy pathways of the pathway arrangement, thereby allowing for themutual interaction of opposite portions of pathway-soured magneticfields produced by the propagation of energy field currents emanatingoutwardly from each set of the complementary conductors. This mutualinteraction maybe a mutual cancellation in embodiments wherein certainpathways may be partially or totally physically shielded from othercomplementary pathways, and may be placed within an influencing distanceof those other complementary pathways. Further, a substantial similarityin size and shape of the respective complementary pathways, includingthe spaced-apart relationship and the interpositioning of a shieldingbetween pathways, and the conductively isolated relationship of thepathways, may contribute to this mutual cancellation effect.Additionally, the shielding operations may be predicated on a relativepositioning of a mating of the paired pathways relative to theconductive electrostatic shielding. At least the complementary energyconditioning functions and electrostatic shielding dynamics discussedherein may operate on various energy propagating in various directionsalong various predetermined pathways, and may operate on circuits havingdynamic operation utilizing the pathway arrangement.

A sub-combination of electromagnetically/electrostatically actuatedimpedance states may develop along or within a pathway arrangement, oralong or within a closely coupled external conductive portionconductively coupled to separate or multiple groupings of shields, tothereby form an energy conditioning circuit. Theseelectromagnetically/electrostatically actuated impedance states maydevelop, for example, because of the energization of one paired set ofpathways of one circuit portion, but not necessarily develop on anotherpaired set of pathways from another circuit portion, for example.

According to an aspect of the present invention, each shield may includea main-body 81. Main-bodies 81 may collectively and conductively coupleto one another and at the same time may substantially immure and shieldthe main-body 80 of the energy pathways. In other embodiments of thepresent invention, the collective shielding main-body 81 may onlypartially immure or shield the pathway main-body 80 s in at least oneportion of the shielding.

According to an aspect of the present invention, a balanced,symmetrical, pathway arrangement may result from the symmetry of certainsuperposed shields, from complementary pathway sizing and shaping,and/or from reciprocal positioning and pairing of the complementarypathways. Manufacturable balanced or symmetrical physical arrangementsof pathways, wherein dynamic energy propagation, interactions, pairingsor match-ups of various dynamic quantities occur, may operate at lessthan a fundamental limit of accuracy of testing equipment. Thus, whenportions of these complementary energy quantities interactsimultaneously, the energy may be beyond the quantifiable range of thetypical testing equipment. Thus, the extent to which the measurement maybe obtained may employ increased controllability, and thereby theelectrical characteristics and the effect on electrical characteristicsmay be controlled, such as by predetermining the desired measurability,behavior or enhancement to be provided, and by a correspondentarrangement of the elements, such as specifically by an arrangement ofthe elements to provide the desired measurability or effect. Forexample, a desired electrical characteristic may be predetermined for adesired enhancement by varying at least a portion of the complementarybalance, size, shape, and symmetry of at least one pathway paring, asset forth herein below and as illustrated in FIGS. 1A, 1B, 1C, 5A and5B, for example.

Thus, the extent of energy interactions, mutual energy propagationtimings and interferences, for example, may be controlled by toleranceswithin the pathway arrangement. A manufacturing process, or computertolerance control, such as semiconductor process control, may controlthese tolerances, for example. Thus, the pathways of an embodiment maybe formed using manufacturing processes, such as passive deviceprocesses, apparent to those skilled in the art. Mutual energypropagation measurements may thereby be cancelled or suppressed by theformation, and process of formation, of the pathway arrangement.

A pathway arrangement may, as set forth hereinabove, include asequentially to positioned grouping of pathways in an amalgamatedelectronic structure having balanced groupings of pathways. The balancedgrouping may include a predetermined pathway architecture having astacked hierarchy of pathways that are symmetrical and complementary innumber, and that are positioned complementary to one another, therebyforming pairs, each of which pair is substantially equidistant from eachside of a centrally positioned shield, wherein each shield may provide asymmetrical balancing point for both each pair pathway and the overallpathway hierarchy as depicted in FIGS. 1A to 41, for example. Thus,predetermined identically sized, shaped and complementary positionedpathways may be present on either side of a centrally positioned shieldfor each separate circuit portion. A total circuit may have itscomplementary portions symmetrically divided into a complementaryphysical format including a reverse-mirror image positioning of pairedshielded, complementary sized and shaped pathways, sandwiching at leastone interposing shield.

According to an aspect of the present invention, each pathway may be,for example, a first interconnect substrate wrapping around, or holding,an integrated circuit wafer, a deposit, an etching, or a resultant of adoping process, and the shield may be, for example, a pathway 55substrate, an energy conditioning embodiment or energy conditioningsubstrate, a deposit, an etching, a resultant of a doping process, andmay have, for example, resistive properties.

Additional elements may be utilized, including conductive andnonconductive elements, between the various pathways. These additionalelements may take the form of ferromagnetic materials orferromagnetic-like dielectric layers, and/or inductive-ferrite 60dielectric derivative materials. Additional pathway structural elementsmay be utilized, including conductive and nonconductive multiplepathways of different conductive material compositions, conductivemagnetic field-influencing material hybrids and conductive polymersheets, various processed conductive and nonconductive laminates,straight conductive deposits, multiple shielding pathway pathwaysutilizing various types of magnetic material shields and selectiveshielding, and conductively doped and conductively deposited on thematerials and termination solder, for example, in addition to variouscombinations of material and structural elements, to provide a host ofenergy conditioning options.

Non-conductor materials may also provide structural support of thevarious pathways, and these non-conductor materials may aid the overallenergized circuit in maintaining the simultaneous, constant anduninterrupted energy propagation moving along the pathways. Dielectricmaterials for example, may include one or more layers of materialelements compatible with available processing technology. Thesedielectric materials may be a semiconductor material such as silicon,germanium, gallium arsenide, or a semi-insulating and insulatingmaterial such as, but not limited to any K, high K and low Kdielectrics.

Pathway and conductor materials may be selected from a group consistingof Ag, Ag/Pd, Cu, Ni, Pt, Au, Pd and other such conductive materials andmetals. Combinations of these metal materials are suitable for thepurposes discussed herein, and may include appropriate metal oxides,such as ruthenium oxide, which, depending on the exigencies of aparticular application, may be diluted with a suitable metal. Otherpathways may be formed of a substantially non-resistive conductivematerial. Any substances and processes that may create pathways fromconductive, non-conductive, semi-conductive material, and/or Mylar filmsprinted circuit board materials, or any substances or processes that maycreate conductive areas such as doped polysilicons, sinteredpolycrystallines, metals, polysilicon silicates, or polysilicon silicidemay be used within or with the pathway arrangement.

An exemplary embodiment of the present invention may utilize an internalshield structural architecture to insure energy balancing configurationswithin the various arrangements, rather than a specific external circuitbalance. This balancing configuration is dependent upon the relativepositioning of all the shields in relationship to the shared andcentrally positioned shield, and the actual paired shields positioned inspecific quantities, to simultaneously provide shielding for theelectrically opposing shielded paired pathways utilized by propagatingenergy. This allows these electrically opposing complementary pathwaysto be located both electrically and physically on the opposite sides ofthe centrally positioned and shared common conductive shield. Thisinterposition of the central and shared shields may create a voltagedivider that divides various circuit voltages in half and that provides,to each of the oppositely paired shielded conductors, one half of thevoltage energy normally expected. The energized circuitry, includingshielded conductors, may be balanced electrically or in acharge-opposing manner and with respect to a centrally positionedshield, to a common and shared pathway, or to each respective, isolatedcircuit system portion. Each common circuit member of an isolatedcircuit system may be attached or coupled to a common area or commonpathway, thereby providing an external common zero voltage. Thus, theembodiment may have multiple sets of shields electrically or physicallylocated between at least one of the various electrically or chargeopposing, shielded pairs or grouped complementary pairs of pathways inan interposed shielding relationship, supported with additional outersandwiching shields, designated herein as -IM that are additionallycoupled and, in part, form the shielding structure.

An exemplary embodiment may also be placed into one or more energycircuits that utilize different energy sources and that may supply oneor more separate and distinct energy-utilizing loads. When energized formultiple energy conditioning operations and for providing simultaneousand effective energy conditioning functions, such as electromagneticinterference filtering, suppression, energy decoupling and energy surgeprotection, each separate and distinct circuit is utilizing the multiplecommonly shared universal shield structure and circuit reference image,or node.

According to an aspect of the present invention, energy-conditioningfunctions may maintain an apparent balanced energy voltage reference andenergy supply for each respective energy-utilizing load within acircuit. This energized arrangement may allow for specific energypropagation utilizing a single, or multiple, isolated pathwayarrangement, and may not require balancing on a single, centralizedshield. A shield may be physically and electrically located between oneor multiple energy sources and one or multiple energy utilizing loads,depending upon the number of separate and isolated pathways. Thusshielding relative, centralized pathways may be in both co-planar andstacked variants of exemplary embodiment.

When the internally positioned paired shielded pathways are subsequentlyattached, or conductively coupled, to externally manufactured pathways,the internally positioned paired shields may be substantially envelopedwithin the cage-like shield structure, thereby minimizing internallygenerated energy strays and parasitics that may normally escape orcouple to an adjacent shielded pathway. These shielding modes utilizepropagating energy to the various pathways and may be separate of theelectrostatic shield effect created by the energization of the shieldstructure. The propagating energy propagating in a complementary mannerprovides energy fields of mutually opposed, mutually cancelled fields asa result of the close proximity of opposite propagation. Thecomplementary and paired pathways may provide an internally balancedopposing resistance load function.

A device according to an aspect of the present invention may mimic thefunctionality of at least one electrostatically shielded transformer.Transformers may be widely used to provide common mode isolationdependent upon a differential mode transfer across the inputs in orderto magnetically link the primary windings to the secondary windings totransfer energy. As a result, common mode voltage across the primarywinding is rejected. One flaw inherent in the manufacturing oftransformers is the propagating energy source capacitance between theprimary and secondary windings. As the frequency of the circuitincreases, so does capacitive coupling, until circuit isolation may becompromised. If enough parasitic capacitance exists, high frequency RFenergy may pass through the transformer and cause an upset in thecircuits on the other side of the isolation gap subjected to thetransient event. A shield may be provided between the primary andsecondary windings by coupling to a common pathway reference sourcedesigned to prevent capacitive coupling between the multiple sets ofwindings. A device according to an aspect of the present inventionimproves upon, and reduces the need for, transformers in circuits. Thedevice may use a physical and relative, common pathway shield tosuppress parasitics and also may use relative positioning of commonpathway shields, a complementary paired pathway layering, the variouscouplings of the pathway layering, and an external conductive couplingto a conductive area per isolated circuit system, in combination withthe various external circuitry, to effectively function as atransformer. If an isolated circuit system is upset by transients, theelectrostatically shielded, transformer function of the device discussedherein may be effective for transient suppression and protection, andmay simultaneously operate as a combined differential mode and commonmode filter. Each set of relative shields and relative conductors may beconductively coupled to at least the same external pathway to provide atransformer functionality for example,

Propagated electromagnetic interference may be the product of bothelectric and magnetic fields. A device according to an aspect of thepresent invention may be capable of conditioning energy that uses DC,AC, and AC/DC hybrid-type propagation, including conditioning energy insystems that may contain different types of energy propagation formatsand in systems that may contain more than one circuit propagationcharacteristic.

In an exemplary embodiment, perimeter conductive coupling material forcoupling or connecting, by conductive joining, of external portions of atypical embodiment into an assembly may be accomplished by conductive ornon-conductive attachments to various types of angled, parallel orperpendicular, as those terms apply relative to at least anotherpathway, conductors known as apertures or blind or non-blind VIAs,passing through, or almost through, portions respectively of anexemplary embodiment. Couplings to at least one or more load(s), such asa portion of an integrated circuit, for one aspect of the invention mayinvolve a selective coupling, or not, to these various types ofconductors, such as apertures and VIAs.

Fabricating a pathway may include forming one or more plated throughhole (PTH) via(s) through one or more levels of a pathway. Electronicpackages commonly include multiple interconnect levels. In such apackage, the invention may include layerings of patterned conductivematerial on one interconnect level that may be electrically insulatedfrom patterned conductive material on another interconnect level, suchas by dielectric material layers.

Connections or couplings between the conductive material at the variousinterconnect levels may be made by forming openings, referred to hereinas vias or apertures, in the insulating portions or layers, that in turncan provide an electrically conductive structure such that the patternedor shaped conductive material portions or pathways from different levelsare brought into electrical contact with each other. These structurescan extend through one or more of the interconnect levels. Use ofconductive, non-conductive or conductively-filled apertures and VIAsallows propagating energy to transverse an exemplary embodiment as ifutilizing a by-pass or feed-through pathway configuration of anembodiment. An embodiment may serve as a support, a system or asubsystem platform that may contain both or either active and passivecomponents layered to provide the benefits described for conditioningpropagated energy between at least one source and at least one load.

An aspect of the present invention may provide a conductive architectureor structure suitable for inclusion in a packaging or an integratedcircuit package having other elements. Other elements may be directlycoupled to the device for simultaneous physical and electrical shieldingby allowing simultaneous energy interactions to take place betweengrouped and energized complementary conductors that are fed by otherpathways. Typical capacitive balances found between at least oneshielding pathway may be found when measuring opposite sides of theshared shield structure per isolated circuit, and may be maintained atmeasured capacitive levels within this isolated circuit portion, evenwith the use of common non-specialized dielectrics or pathway conductivematerials. Thus, complementary capacitive balancing, or tolerancebalancing characteristics, of this type of electrical circuit due toelement positioning, size, separations and attachment positioning allowan exemplary embodiment having an isolated circuit system manufacturedat 3% capacitive tolerance, internally, to pass to a conductivelycoupled and energized isolated circuit system a maintained andcorrelated 3% capacitive tolerance between electrically opposing andpaired complementary pathways of each respective isolated circuitsystem, with respect to the dividing shield structures placed into theisolated circuit system.

An exemplary embodiment may allow utilization of relatively inexpensivedielectrics, conductive materials and various other material elements ina wide variety of ways. Due to the nature of the architecture, thephysical and electrical dividing structure created may allow the voltagedividing and balancing among the grouped, adjacent elements, and mayallow for the minimization of the effect of material hysteresis andpiezoelectric phenomenon to such a degree that propagating energynormally disrupted or lost to these effects may be essentially retainedin the form of active component switching response time, as well asinstantaneous ability to appear to the various energy-utilizing loads asan apparent open energy flow simultaneously on both electrical sides ofa pathway connecting or coupling from an energy source to a respectiveload, and from the load back to the source.

A structured layer may be shaped, buried within, enveloped by, orinserted into various electrical systems and sub-systems to perform lineconditioning or decoupling, for example, and to aid in or to allow for amodifying of an electrical transmission of energy to a desired orpredetermined electrical characteristic. Expensive, specialized,dielectric materials that attempt to maintain specific or narrow energyconditioning or voltage balancing may no longer be needed for bypass,feed through, or energy decoupling operations for a circuit.

A device according to an aspect of the present invention may, as setforth hereinabove, be placed between each isolated circuit and a pairedplurality of pathways or differential pathways. This exemplary devicemay operate effectively across a broad frequency range, as compared to asingle discrete capacitor or inductor component, and may continue toperform effectively within an isolated circuit system operating beyond,for example, a GHz.

As set forth hereinabove, the exemplary device may perform shieldingfunctions in this broad frequency range. A physical shielding of paired,electrically opposing and adjacent complementary pathways may resultfrom the size of the common pathways in relationship to the size of thecomplementary pathways, and from the energized, electrostaticsuppression or minimization of parasitics originating from thesandwiched complementary conductors and preventing external parasitics.Further, the positioning of the shielding, relative to shielding that ismore conductive, may be used to protect against inductive energy and“H-Field” coupling. This technique is known as mutual inductivecancellation.

Parasitic coupling is known as electric field coupling. The shieldingfunction discussed hereinabove provides primary shielding of the variousshielded pathways electrostatically against electric field parasitics.Parasitic coupling involving the passage of interfering propagatingenergy because of mutual or stray parasitic energy originating from thecomplementary conductor pathways may be thereby suppressed. A deviceaccording to an aspect of the present invention may, for example, blockcapacitive coupling by enveloping oppositely phased conductors in theuniversal shield architecture with stacked conductive hierarchicalprogression, thereby providing an electrostatic or Faraday shield effectwith respect to the pathway positioning as to the respective layeringand position, both vertically and horizontally, of the pathways. Theshielding pathway architecture may be used to suppress and preventinternal and external parasitic coupling between potentially noisyconductors and victim conductors, such as by an imposition of a numberof common pathway layers that are larger than the smaller pairedcomplementary pathways, but that are positioned between each of thecomplementary pathway conductor pairs to suppress and to contain thestray parasitics.

Further, as set forth hereinabove, positioning of the shielding,relative to shielding that is more conductive, may be used againstinductive energy and “H-Field” coupling. This cancellation isaccomplished by physically shielding energy, while simultaneously usinga complementary and paired pathway positioned to allow for the insettingof the contained and paired complementary pathways within an area sizecorrespondent to the shield size. A device according to an aspect of thepresent invention is adapted to use shields separately as internalshields or groupings, thereby substantially isolating and sandwichingpairs of electrically opposing complementary pathways, and therebyproviding a physically tight or minimized energy and circuit looppropagation path between each shield and the active load. Closeproximity of shields and non-shields may allow energy along shields evenif a direct electrical isolation exists because of 801 material type orthe spacing. Flux cancellation of propagating energy along paired andelectrically opposing or differential pathways may result from spacingof pathways apart by a very small distance for oppositely phasedelectrically complementary operations, thereby resulting in asimultaneous stray parasitic suppression and containment functionattributable to tandem shielding, and thereby enhancing energyconditioning.

In attaining minimum areas for various current loops in an isolatedcircuit system, additional shielding energy currents may be distributedaround component shielding architectures. A plurality of shields asdescribed hereinabove may be electrically coupled as either an isolatedcircuit's reference node, or chassis ground, and may be relied on as acommonly used reference pathway for a circuit. Thus, the various groupsof internally paired, complementary pathways may include propagatingenergy originating from one or more energy sources propagating alongexternal pathways coupled to the circuit by a conductive material.Energy may thus enter the device, undergo conditioning, and continue toeach respective load.

The shielding structure may allow for a portion of a shield to operateas the pathway of low impedance for dumping and suppressing, as well asat least partially blocking return of unwanted electromagneticinterference noise and energy into each of the respective energizedcircuits. In an embodiment, internally located shields may beconductively coupled to a conductive area, thereby adaptively utilizingshielding structure for low impedance dumping and suppressing and atleast partially blocking return blocking of unwanted electromagneticinterference noise and energy. Additionally, another set of internallylocated shields may be conductively coupled to a second conductive area,thereby utilizing shields for low impedance dumping, suppressing and atleast partially blocking the return of unwanted electromagneticinterference noise and energy. The conductive areas may be electricallyor conductively isolated from one another.

Simultaneous suppression of energy parasitics may be attributed to theenveloping shielding pathway structure, in combination with thecancellation of mutually opposing energy fields, and may be furtherattributed to the electrically opposing shielded pathway pathways andpropagating energy along the various circuit pathways interacting withinthe various isolated circuits to undergo a conditioning effect takingplace upon the propagating energy. This conditioning may includeminimizing effects of H-field energy and E-field energy throughsimultaneous functions, such as through isolated circuits that containand maintain a defined electrical area adjacent to dynamic simultaneouslow and high impedance pathways of shielding in which various pairedpathways have their respective potentials respectively switching as aresult of a given potential located on a shielding and usedinstantaneously and oppositely by these pairings with respect to theutilization by energy found along paired routings of the low and highimpedance shields.

The various distance relationships created by the positional overlappingof energy routings within the isolated circuits combine with the variousdynamic energy movements to enhance and cancel the various degrees ofdetrimental energy disruptions normally occurring within activecomponents or loads. The efficient energy conditioning functionsoccurring within the passive layering architecture allow for developmentof a dynamic “0” impedance energy “black hole”, or energy drain, along athird pathway coupled common to both complementary pathways and adaptedto allow energy to be contained and dissipated upon the shielding,within the various isolated circuits and attached or conductivelycoupled circuits. Thus, electrically opposing energies may be separatedby dielectric material and/or by an interposition shield structure,thereby allowing dynamic and close distance relationship within aspecific circuit architecture, and thereby taking advantage ofpropagating energy and relative distances to allow for exploitation ofmutual enhancing cancellation phenomenon and an electrostaticsuppression phenomenon to, exponentially allow layered conductive anddielectric elements to become highly efficient in energy handlingability.

According to an aspect of the present invention, a device may utilize asingle low impedance pathway or a common low impedance pathway as avoltage reference, while utilizing a circuit maintained and balancedwithin a relative electrical reference point, thereby maintainingminimal parasitic contribution and disruptive energy parasitics in theisolated circuit system. The various attachment schemes described hereinmay allow a “0” voltage reference, as discussed hereinabove, to developwith respect to each pair or plurality of paired complementaryconductors located on opposite sides of the shared central shield,thereby allowing a voltage to be maintained and balanced, even withmultiple Simultaneous Switching Operations states among transistor gateslocated within an active integrated circuit, with minimal disruptiveenergy parasitics in an isolated circuit.

Shields may be joined using principals of a cage-like conductive shieldstructure to create one or more shieldings. The conductive coupling ofshields together with a larger external conductive area may suppressradiated electromagnetic emissions and as a larger area provides agreater conductive area in which dissipation of voltages and surges mayoccur. One or more of a plurality of conductive or dielectric materialshaving different electrical characteristics may be maintained betweenshields. A specific complementary pathway may include a plurality ofcommonly conductive structures performing differentially phasedconditioning with respect to a “mate”, or paired, plurality ofoppositely phased or charged structures forming half of the total sum ofmanufactured complementary pathways, wherein one half of thecomplementary pathways forms a first plurality of pathways, and whereinthe second half forms a second plurality of pathways. The sum of thecomplementary pathways of the first and the second plurality of pathwaysmay be evenly separated electrically, with an equal number of pathwaysused simultaneously, but with half the total sum of the individualcomplementary pathways operating from, for example, a range of 1 degreeto approximately 180 degrees electrically out of phase from theoppositely positioned groupings. Small amounts of dielectric material,such as microns or less, may be used as the conductive materialseparation between pathways, in addition to the interposing shield,which dielectric may not directly physically or conductively couple toany of the complementarily operating shielded pathways.

An external ground area may couple or conductively connect as analternative common pathway. Additional numbers of paired externalpathways may be attached to lower the circuit impedance. This lowimpedance phenomenon may occur using alternative or auxiliary circuitreturn pathways.

A shield architecture may allow shields to be joined together, therebyfacilitating energy propagation along a newly developed low impedancepathway, and thereby allowing unwanted electromagnetic interference ornoise to move to this created low impedance pathway.

Referring now to FIG. 1A through FIG. 5B, which generally show variouscommon principals of both common and individual variants of an exemplaryembodiment configured in a co-planar variant (FIGS. 1A-4I) and a stackedvariant (FIGS. 5A and 5B).

In FIG. 1A, there are shown relative locations of the various pathwayextensions disclosed according to an aspect of the present invention. Aportion of a relative balanced and complementary-symmetrical arrangementutilizing a center shielding pathway designated 8“XX”-“X”M is adapted inthe arrangement as the fulcrum of balanced conductive portions in aco-planar variant. A pathway arrangement including at least a first anda second plurality of pathways, wherein the first plurality has at leastone pair of pathways arranged electrically isolated from each other andorientated in a first complementary relationship, is illustrated.Additionally, at least a first half of the second plurality is arrangedelectrically isolated from a second half of the second plurality,wherein at least two pathways of the second plurality are electricallyisolated from the pathways of first plurality. The pathway arrangementmay also include a material having properties, such as dielectric,ferromagnetic, or varistor for example, spacing apart pathways of thepathway arrangement. The pathways of the first half of the secondplurality are electrically coupled to one another, and the pathways ofthe second half of the second plurality are electrically coupled to oneanother. A total number of pathways of the first half of the secondplurality may be an odd number greater than one, and a total number ofpathways of a second half of the second plurality may also be an oddnumber greater than one. According to an aspect of the presentinvention, the pathways of the first half of the second plurality arepositioned in a first superposed alignment, while the pathways of thesecond half of the second plurality are positioned in a secondsuperposed alignment, with the first and second superposed alignments ina mutual superposed alignment herein defined as a co-planar arrangement.

In a non co-planar arrangement, the pathways of the first half of thesecond plurality may be positioned in a first superposed alignment, andthe pathways of the second half of the second plurality may bepositioned in a second superposed alignment, with the first and secondsuperposed alignments in arrangement one atop the other. In onearrangement, at least four pathways are electrically isolated.

An illustrative embodiment of the present invention may include at leastthree pluralities of pathways, including a first plurality of pathwaysand a second plurality of pathways. The first and second pluralities ofpathways may include pathway members of the first plurality having anequal and opposite pathway member found in the second plurality ofpathways. Members of the first and second pluralities of pathways may besubstantially the same size and shape, and may be positionedcomplementary, and may also operate in an electrically complementarymanner. Thus, the pairings of the first and second pluralities ofpathways may result in identical numbers of members of the first andsecond pluralities of pathways. An exemplary embodiment may provide atleast a first and a second shield allowing for development of individualisolated low circuit impedance pathways. Structurally, the shields maybe accomplished by a third plurality of pathways and a fourth pluralityof pathways. Each shielding plurality may include shields of equal sizeand shape. Each of the third and fourth plurality of pathways may beconductively coupled. Conductive coupling may be accomplished by avariety of methods and materials known to those possessing an ordinaryskill in the pertinent arts. Thus, when the third and a fourth pluralityare grouped as two sets of shields utilizing the first and secondplurality receiving shielding, the third and fourth pluralities may becoupled to a common pathway to develop a low circuit impedance pathwayfor energy propagation for conditioning of the circuit energy.

Pathways may additionally be arranged in a bypass arrangement, such thatwhen placed face to face, main-body pathways 80 may be alignedsuperposed, with the exception of any pathway extensions such as 812NNE,81NNE, 812SSW and 811SSW of the lower sub-circuit portion, for example,shown as mirror images depicted in FIG. 5A and FIG. 5B, for example.

Within the pluralities, individual pathway members may be ofsubstantially the same size and shape and may be conductively coupled.However, individual pathway members of one plurality may not beconductively coupled to members of a different plurality of pathways.There may be situations wherein members of one plurality may beconnected to members of a different plurality, such as wherein a firstplurality of shields and a second plurality of shields are externallycoupled to the same conductor.

Common elements may include energy flow in accordance with conceptualenergy indicators 600, 601, 602, 603 depicting the dynamic energymovements in co-planar shielded by-pass pathways, such as those shown inFIG. 1A-1C. An embodiment may provide for at least multiple shields fordevelopment of multiple isolated low circuit impedance pathways formultiple circuits.

Referring still to FIG. 1A, pathways may be shielded by the relative,common pathways, and may include a main-body pathway 80 with at leastone pathway extension 812“X”. The shields shown include a main-bodyshield pathway 81 with at least one pathway extension designated99“X”/79“X”. The shields may sandwich and envelope the main-body 799,including a conductive inner pathway formed of conductive materials fromthe family of noble or base metals traditionally used in co-firedelectronic components or conductive material, such as Ag, Ag/Pd, Cu, Ni,Pt, Au, Pd, or combination materials such as metal oxide and glass frit.A capacitance and a resistance value may be achieved in one family ofpathways, as described hereinabove, such as by use of ruthenium oxide asthe resistive material and Ag/Pd as the conductive material. Further,variations in pathway geometry may yield different resistance andcapacitance values. Variations may be achieved by altering the materialsfrom which the pathways are made. For example, a conductive metal, suchas silver, may be selectively added to the metal oxide/glass fritmaterial to lower the resistance of the material.

A plurality of pathways, 865-1 and 865-2, are shown positioned co-planarand spaced apart on a same portion of material 801. Each pathway of theco-planar pathways 865-1 and 865-2, may be formed of conductive material799, or a hybrid of conductive material and another material, hereindesignated as 799“x”. Each co planar pathway 865-1 and 865-2 may also beformed as a bypass pathway, wherein each pathway includes a main-bodypathway 80 having a corresponding main-body edge and perimeter, 803A and803B, respectively and at least one pathway contiguous extension 812“X”.Each co-planar pathway 865-1 and 865-2, may include at least one pathwaycontiguous extension 812SSW and 811SSW with a portion of the main-bodyedge 803A and 803B extending therefrom. Extension 812“X” is a portion ofthe pathway material formed in conjunction with a main-body pathway 80from which it extends. Main-body pathway 80, an 812“X” may be found asan extension of material 799 or 799“x” extending beyond an acceptedaverage perimeter edge 803“X”. Extensions 812“X” and 79“X” may be foundrespectively positioned as a contiguous portion of the pathway fromwhich it is formed. Each main-body pathway may have edge 803A, 803Bpositioned relative and spaced apart a distance 814F from the embodimentedge 817. Embodiment edge 817 may include a material 801. Co-planarmain-body pathway's edge 803“x” may be positioned and spaced apart adistance 814J. Pathway extensions 812SSW and 811SSW may conductivelycouple a respective pathway main-body 80 to an outer pathway 890SSW and891SSW, which may be positioned at edge 817. The co-planar arranged,main-body pathway 80 may be positioned “sandwiched” between the area ofregistered coverage of two layering of co-planar, main-body pathway 81s.

Combining mutually opposing fields causes a cancellation or minimizationeffect. The closer the complementary, symmetrically oriented shields,the better the resulting mutually opposing cancellation effect onopposing energy propagation. The more superposed the orientation of thecomplementary, symmetrically oriented shields is, the better theresulting suppression of parasitics and cancellation effect.

Referring still to FIG. 1A, the edges of the plurality of co-planarshields may be represented by dotted lines 805A and 805B. Main-bodypathways 81 of each of the plurality of shields are larger than asandwiching main-body pathway 80 of any corresponding sandwichedpathway. This may create an inset area 806 relative to the positions ofthe shields and remaining pathways. The size of main-bodies 80 and 81may be substantially similar, and thus the insetting positioningrelationships may be minimal in certain embodiments. Increased parasiticsuppression may be obtained by insetting pathways, including a main-body80, to be shielded by larger pathway main-body 81 s. For example, aninset of a main-body 80 of pathways 865-1 inset may be separated adistance of 1 to 20+32 times the spacing provided by the thickness ofthe material 801 separating pathway 865-1 and adjacent center co-planarpathway 800-IM-1, as illustrated in FIG. 1B.

Plurality of co-planar shield edges 805A and 805B may be positioned andspaced apart a distance 814K, and may be a distance 814 relative toedges 805A and 805B and the edge 817. Other distances 814J relative fromeither edges 803A and 803B may be provided.

Further, distance 814F may be present between one 803“X” and an edge817. Each co-planar shield may include a plurality of contiguous pathwayextension portions, such as, for example, portions 79NNE, 79SSE, 99NNEand 99SSE, extending from the plurality of co-planar shield edges 805Aand 805B. Plurality of co-planar shields may include a plurality ofouter pathway material 901NNE, 901SSE, 902NNE and 902SSE positioned atthe edge 817. Conceptual energy indicators 602 represent the variousdynamic energy movements within ro the co-planar pathways 865-1 and865-2. Unwanted energy may be transferred to the co-planar shields inaccordance with the provision by the shields providing for a lowimpedance pathway, which shields may additionally be electricallycoupled to another pathway or conductive area.

Referring now to FIGS. 1B and 1C, layer sequences are illustrated for afirst plurality of co-planar pathways 865-1, 865-2, a second pluralityof co-planar pathways 855-1, 855-2, and a third plurality of co-planerpathways 825-1-IM, 825-2-IM, 815-1, 815-2, 800-1-IM, 800-2-IM, 810-1,810-2, and 820-1-IM, 820-2-IM. The first, second, and third pluralitiesmay be stacked to form an embodiment 3199, 3200, 3201. The thirdplurality of co-planar pathways may provide shielding. Main-bodies 81 ofthe plurality of co-planer shields 825-1-IM, 825-2-IM; 815-1, 815-2;800-1-IM, 800-2-IM; 810-1, 810-2; and 820-1-IM, 820-2-IM may besubstantially similar in size and shape, and may be spaced apart inco-planar locations on different layers of material 801. The firstplurality of co-planar pathways 865-1 and 865-2 may have at least thecorresponding, opposing, and complementary second plurality of co-planarpathways 855-1 and 855-2. These first and second pluralities ofco-planar pathways, when oriented face to face, may have main-bodypathways 80 s co-registered and aligned except for the variouscontiguous pathway extensions 812“X”, 811“X”. As shown in FIGS. 1B and1C, a pair of outer co-planar pathways 820-1-IM, 825-1-IM may serve aspathway shields, thereby improving the shielding effectiveness of theother conductively coupled pluralities of pathways with a main-body 81s.

As illustrated in the varied embodiments 3199, 3200, 3201, the locationof extensions 79NNE, 79SSE, of shields 825-1-IM, 815-1, 800-1-IM, 810-1,and 820-1-IM and extensions 99NNE, 99SSE of the shields 825-2-IM, 815-2,800-2-IM, 810-2, and 820-2-IM, may be varied. In FIG. 1B, for example,extensions 79NNE and 99NNE may be arranged spaced apart, diagonally fromextensions 79SSE and 99SSE and on opposite sides of shield main-body 81.In FIG. 1C, for example, extensions 79NNE and 99NNE may be arrangedspaced apart in line with extensions 79SSE and 99SSE on opposite sidesof shield main-body 81. In FIG. 1B, extensions 812NNE and 811NNE may bearranged spaced apart, extending toward the same edge 812 of layer ofmaterial 801, and extensions 812SSW and 811SSW may be arranged spacedapart, each extending toward the opposite edge 812 of layer of material801. In FIG. 1C, pathways 865-1 and 865-2 may be mirror images, asdiscussed hereinabove. Comparably to FIG. 1B, extensions 812NNE and811NNE may be arranged spaced apart, extending toward opposite edges 817of layer of material 801. Extensions 812SSW and 811SSW may be arrangedspaced apart, extending toward the opposite edge of layer of material801, such that extensions 812NNE and 811SSW extend toward opposite edges812“X” of the respective layer of material 801.

Referring now to FIGS. 2A and 2B, FIG. 2A illustrates a schematic planview of a an embodiment of FIG. 2B according to an aspect of the presentinvention. FIG. 2B depicts a pathway arrangement including a layout of afirst, a second, a third, a fourth, a fifth, a sixth, a seventh, aeighth, a ninth and a tenth pathway, wherein at least the third and thefourth pathway, for example, may be co-planar and arranged spaced apartfrom each other. FIG. 2B illustrates the first and the second pathwayarranged below the third and the fourth pathway, and the fifth and thesixth pathway arranged above the third and the fourth pathway, and theseventh and the eighth pathway arranged above the fifth and the sixthpathway, and the ninth and the tenth pathway, arranged above the seventhand the eighth pathway. These pathways have various respective internalcontiguous pathway extensions 812“X”, 811“X”, 79“X” and 99“X”, and maybe discrete components having the same minimal numbers of layering.Internal contiguous pathway extensions 812“X”, 811“X”, 79“X” and 99“X”,and conductively coupled external pathways 890“X”, 891“X” 802“X” and902“X”, may be coupled to the inner pathway of the plurality ofco-planar pathways of the main-body pathway 80 and 81.

Referring now to FIGS. 3A and 3B, in FIG. 3A there is shown a schematicplan view of an embodiment of FIG. 3B, wherein outer pathways may beselectively conductively coupled in at least two isolated circuitportions. FIG. 3B depicts an pathway arrangement including a minimallayout of a first, a second, a third, a fourth, a fifth, a sixth, aseventh, a eighth, a ninth and a tenth pathway, wherein at least thethird and the fourth pathway, for example, are co-planar and arrangedspaced apart from each other. The device shown in FIG. 3B may have thefirst and the second pathway arranged below the third and the fourthpathway, and the fifth and the sixth pathway arranged above the thirdand the fourth pathway, and the seventh and the eighth pathway arrangedabove the fifth and the sixth pathway, and the ninth and the tenthpathway arranged above the seventh and the eighth pathway. Thesepathways have various respective internal contiguous pathway extensions812“X”, 811“X-”, 79“X” and 99“X”, and may be discrete components havingthe same minimal number of layering.

Referring now to FIG. 3C, a plan view of a shield according to an aspectof the present invention is illustrated. The embodiment depicted in FIG.3C includes at least one additional pathway, as compared to the deviceof FIG. 3B. This additional pathway 1100-IM“X” may be one of at least aplurality of shields in the stack of pathways, which shields may spanacross the two circuit portions. Pathway 1100-IM“X” may be one of atleast two outer sandwiching shields in the stack of pathways. Shieldsmay span across the two circuits by adding a centrally arranged100-IM“X” pathway electrically coupled to the outer 1100-IM“X” shields.Pathways 1100-IM“X” may have at least one extension, and are illustratedwith two extensions 1099NNE and 1099SSE, and may allow for sandwichingshields for all of the pathways within the present invention. At leastthree shields may be coupled together and may include a centering shielddividing an energy load or energy source of an isolated circuit ordividing two isolated circuits.

A shield 00GS may be electrically isolated from other shields and may bearranged to effect an energy propagation of an isolated circuit. Anisolated circuit may be sandwiched by a shield. A shield may beelectrically coupled to a conductive area that is isolated from anyother conductive areas thereby effecting an energy propagation.

FIGS. 4A-4I depict assembled components of various embodiments accordingto aspects of the present invention. The arrangements of FIG. 4A to FIG.41 may include minimal layouts of a first, a second, a third, a fourth,a fifth, a sixth, a seventh, a eighth, a ninth and a tenth pathway,wherein at least the third and the fourth pathway, for example, areco-planar and arranged spaced apart from each other. The first and thesecond pathway may be arranged below the third and the fourth pathway,and the fifth and the sixth pathway may be arranged above the third andthe fourth pathway, and the seventh and the eighth pathway may bearranged above the fifth and the sixth pathway, and the ninth and thetenth pathway may be arranged above the seventh and the eighth pathway.These pathways have various respective internal contiguous pathwayextensions 812“X”, 811“X”, 79“X” and 99“X”, and may be an assembledfinal discrete component, for example.

Referring to FIG. 5A, there is shown a stacking of multiple, non-sharedcircuits ho including groups of pathways according to an aspect of thepresent invention. Included in FIG. 5A is a marker 1000 showing acontinuation of the stacking arrangement to the next column of FIG. 5A.Conceptual energy indicators 600, 601, 602, 603 indicate energy flow.Material 799 may be deposited on material 801 for component 6900 shieldsdesignated 815-1, 800-1, 810-1-IM, 815-2, 800-2-IM, and 810-2. Shields810-A and 810-B are separated shields of at least part of an isolatedcircuit system. Shields 815-A and -B are separated shields of at leastpart of an isolated circuit system. Shields 820-A and 820-B areseparated shields at least part of an isolated circuit system. Shields825-A and 825-B are separated shields at least part of an isolatedcircuit system. Conductors 855-1 and 855-2 are separated and shieldedpathways in bypass configuration. Conductors 865-1 and 865-2 areseparated 70 and shielded pathways in bypass configuration. In FIG. 5A,a pathway arrangement is depicted including at least six orientations ofpathways of two types of pathways, wherein each orientation of thepathways of the at least six orientations of pathways providesconductive isolation from the remaining orientations of pathways.

Referring to FIG. 5B, there is shown a stacked shield structureaccording to an aspect of the present invention. FIG. 5B depicts anembodiment similar to that of FIG. 5A, wherein two sets of 855“X” and865“X” pathways are omitted for purposes of clarity, and wherein theshields of FIG. 5A are oriented in flip-flop for each relative set of855“X” and 865“X” pathways. The 79“X” pathway extensions may be rotated90 degrees relative to the various pathway extensions 811“x” and 812“X”.A dynamic result of this configuration, as illustrated by the conceptualenergy indicators, may be enhanced by nulling the extensions of the twosets of 855“X” and 865“X” pathways of the two isolated circuits, and byrelatively positioning the shield of each isolated circuit pairing 855Aand 865A approximately 90 degrees null to the various pathway extensionsof 855B and 865B.

Referring to FIG. 5B, there is shown a stacked shield structureaccording to an aspect of the present invention. FIG. 5B depicts anembodiment similar to that of FIG. 5A, wherein two sets of 855“X” and865“X” pathways are omitted for purposes of clarity, and wherein theshields of FIG. 5A are oriented in flip-flop for each relative set of855“X” and 865“X” pathways. The 79“X” pathway extensions may be rotated90 degrees relative to the various pathway extensions 811 “x” and812“X”. A dynamic result of this configuration, as illustrated by theconceptual energy indicators, may be enhanced by nulling the extensionsof the two sets of 855“X” and 865“X” pathways of the two isolatedcircuits, and by relatively positioning the shield of each isolatedcircuit pairing 865B and 865A approximately 90 degrees null to thevarious pathway extensions of 865B and 865A.

As discussed hereinabove, in an embodiment of the present invention,multiple complementary or paired shielded pathways may include the firstand second pluralities of pathways. Energy may utilize the variouspaired, feed-through or bypass pathway layers in a generally paralleland even manner, for example. Pathway elements may include non-insulatedand conductive apertures, and conductive through-VIAs, to providepropagating energy and maintain a generally non-parallel orperpendicular relationship, and additionally maintain a separateelectrical relationship with an adjoining circuit. These pathways maymaintain balance internally, and may facilitate an electrical oppositionalong opposing complementary pairings. This relationship amongcomplementary pairs of pathways may occur while the pathways and theenergy are undergoing an opposite operational usage within the shieldingstructure attached externally.

Referring now to FIG. 5C, there is shown a relative plan view of astacked multiple, non-shared circuit network having VIAs and includinggroups of pathways according to an aspect of the present invention. Thedevice according to an aspect of the present invention depicted in FIG.5C includes a hole-through energy conditioner. Hole-through energyconditioners may be formed such that many of the energy propagationprincipals disclosed herein are retained, including the use of multiplesets of shields for energy conditioning possessing. FIG. 5C, furtherdepicts null pathway sets with pathway arrangement 6969. Pathwayarrangement 6969 is similar to FIG. 5B, with the absence of pathwayextensions 79“X”, 811“x” and 812“X”, and with the substitution of8879“X”, 8811“X” and 8812“X” VIAs functioning from a different directionrelative to the main-body 80 and 81.

Referring still to FIG. 5C, during the manufacturing process, conductiveholes 912, VIAS or conductive apertures may be used to interconnect 8806an integrated circuit, and may be formed through one or more pathwaylayers using mechanical drilling, laser drilling, etching, punching, orother hole formation techniques. Each specific interconnection 8806 mayenable various pathways to be electrically connected or insulated. Eachspecific interconnection 8806 may extend through all layers of pathwayarrangement 6969, or may be bounded above or below by one or morelayers. Pathway arrangement 6969 may include an organic substrate, suchas an epoxy material, or patterned conductive material. If an organicsubstrate is used, for example, standard printed circuit board materialssuch as FR-4 epoxy-glass, polymide-glass, benzocyclobutene, Teflon,other epoxy resins, or the like could be used in various embodiments. Inalternate embodiments, a pathway arrangement could include an inorganicsubstance, such as ceramic, for example. In various embodiments, thethickness of the levels may be approximately 10-1000 microns.Interconnections 8806 between the various conductive layers may also beformed by selectively removing dielectric and conductive materials,thereby exposing the conductive material of the lower conductive layers904, and by filling the holes so formed by the removal with a conductivepaste 799A or electrolytic plating 799B, for example.

Interconnections 8806 may couple exposed conductive layers to a relativeside of the pathway arrangement 6969. Interconnections 8806 may take theform of pads or lands to which an integrated circuit may be attached,for example. Interconnections 8806 may be formed using known techniques,such as by filling the selectively removed portions of dielectric withconductive paste, electrolytic plating, photolithography, or screenprinting, for example. The resulting pathway arrangement 6969 includesone or more layers of patterned conductive material 904, separated bynon-conducting layers, and interconnected by interconnects 8806.Different techniques may be used to interconnect and isolate the variouslayers of patterned conductive material 799. For example, rather thanforming and selectively removing portions of the various conducting 799and non-conducting layers 801, openings between the various layers maybe included by selectively adding the desired portions of the conducting799 and non-conducting layers 801. Removal techniques, such as chemicalmechanical planarization, may be used to physically abrade away multiplelayers of different types of conducting and non-conducting materials,resulting in the desired openings for various interconnects.

Pathway arrangement 6969 may be configured using a multi-aperture,multilayer energy conditioning pathway set, with a substrate formatadapted to condition propagating energy. Pathway arrangement 6969 maycondition propagating energy by utilizing a combined energy conditioningmethodology of conductively filled apertures, known in the art as VIAs8879“X”, 8811“X” and 8812“X”, in combination with a multi-layer commonconductive Faraday cage-like shielding technology with immuredpropagational pathways.

Interconnecting pathway arrangement and an IC may be achieved with wirebonding interconnection, flip-chip ball-grid array interconnections,microBall-grid interconnections, combinations thereof, or any otherstandard industry accepted methodologies. For example. a “flip chip”type of integrated circuit, meaning that the input/output terminationsas well as any other pathways on the chip may occur at any point on itssurface. After the IC chip is prepared for attachment to pathwayarrangement 6969, the chip may be flipped over and attached, by solderbumps or balls to matching pads on the top surface of pathwayarrangement 6969. Alternatively, an integrated circuit may be wirebonded by connecting input/output terminations to pathway arrangement6969 using bond wires to pads on the top surface of pathway arrangement6969.

The circuits within pathway arrangement 6969 may act as a source to loadpathway arrangement requiring capacitance, noise suppression, and/orvoltage dampening. This capacitance may be provided by formation of thecapacitance developed and embedded within pathway arrangement 6969. Thiscapacitance may be coupled to the integrated circuit loads using apaired pathway and the shield, as described above. Additionalcapacitance may be provided to a circuit electrically coupled to anintegrated circuit to provide voltage dampening and noise suppression.Close proximity of off-chip energy sources may provide a capacitanceeach along the low inductance path to the load. Common shieldingpathways may be utilized as the “0” voltage circuit reference node forboth off-chip energy sources the common conductive interposer energypathway configurations.

Pathway arrangement 6969 may be connected to an integrated circuit bycommonly accepted industry connection methods and couplings 799A and799B, including Bumpless Build-Up Layer (BBUL) packaging. Thistechnology enables higher performance, thinner and lighter packages, andlowers power consumption. In a BBUL package, the silicon die or IC isembedded in a package with a pathway arrangement operable as a firstlevel interconnect. Thus, the BBUL package as a whole is not justattached to one surface of the IC. For example, electrical connectionsbetween the die and one or more of the various shields and the packagemay be made with copper lines, not necessarily C4 solder bumps. Thesefeatures combine to make the package thinner and lighter than other ICpackages, while delivering higher performance and reducing powerconsumption. BBUL may enhance the ability of a manufacturer to couplemultiple silicon components to pathway arrangement 6969. Shieldedpathways 8811, 8812, and 8879 may be electrically connected betweenrespective energy sources and respective load of the IC by commonindustry methodologies, thereby allowing for conditioning of propagatingenergy. Shields 8879 may conductively coupled to a shield including1055-2. A shield and its other conductive portions including 8811 and8812 may be electrically coupled to a respective complementary pathwaywhich poses no polarity charge of significance before hook-up, therebypreventing each layer 8811 and 8812 from changing energy propagationdirection functions, such preventing layer 8811 and 8812 from changingfrom input and output to output and input, respectively, as isunderstood by those possessing an ordinary skill in the pertinent arts.

For stacked variants depicted in FIGS. 5A, 5B and 5C, adding threepathways 1100-IM-“X”, including one between 810-1 and 815-2, designatedas 1100-IM-“C”, may bisect a balanced symmetry of the total number ofpathways located into equal numbers on opposite sides of 1100-IM-“C”.The addition of 1100-IM-1 and 1100-IM-2, electrically coupled to1100-IM-C, creates a common or a shield structure (not all shown).Shields of a shield structure may be of substantially the same size ornot. Shields may or may not be physically isolated from any othershields for any one or more embodiments of the present invention. Thus,shields may or may not be electrically or conductively isolated from anyother shields for any one or more embodiments of the present invention.

An odd number of shields may be coupled together thereby allowingformation of a common reference or node utilizing all other shields. Thenumber of shields 1100-IM-“X” is not confined to using extensions1099NNE and 1099SSE such as shield 00GS, as any number of extensions inalmost any direction may be used to facilitate a coupling. A relativebalanced and complementary-symmetrical arrangement may be formed withrespect to a center shield 8“XX” or shield 800/800-IM for a as thearrangement fulcrum of balanced conductive portions. At least a partialflux field cancellation of energy propagating along or between pairedand electrically opposing complementary pathways occurs in this balancedbut shifted embodiment. Further, simultaneous stray energy parasitics,complementary charged suppression, physical and electrical shieldingcontainment and a faraday effect may also occur. This result is achievedbecause the magnetic flux energies travel at least partially along theshield wherein the RF return path is parallel and adjacent to acorresponding pathway. Thus, the magnetic flux energy may be measured orobserved relative to a return

Shifted pathways may be in relative balance and complementarily andsymmetrically positioned with respect to center shields, such as shields800/800-“X”-IM, and may include a relatively shifted, balanced,complementary, and symmetrical arrangement of predetermined shields andpathways complementarily sandwiched around a centrally positionedshield, such as 800/800-IM, for example.

The exemplary embodiments of FIGS. 1A, 1B, 1C, through FIG. 41, forexample may include these ‘shifted’ embodiments. These shiftedembodiments may include a multiplicity of layers having a shielding, apathway, a shielding, an pathway, and a shielding. Each of thesemultiplicity of layers may be centered and complementary about a centershield 800/800-“X”-IM, such as for co-planar variants, and the entiremultiplicity of layers may be centered about a main center shield.Complementarity and balance may be maintained about the center shield,and the main center shield, although individual shields may be shiftedto create discrete imbalances as between a given matched pathway pair,for example. Shifting may expose a portion of at least one pathwayoutside the perimeter of the superposed shielding, thereby allowing forparasitics and thereby varying, for example, impedance characteristics.

For example, a given pathway may be shifted 5 points to the left. Thisshifting may be accounted for in the matched pairs about a centershield, and, consequently, either an adjacent matched pair pathway ofopposing polarity may be shifted 5 points, or 5 adjacent pathways ofopposite polarity may each shift 1 point, thereby maintainingcomplementarity and balance. Further, pathways may remain within theperimeter of the superposed shielding, and nonetheless be shiftedthereunder. Such a shifting under the shielding may, nonetheless, makedesirable a balancing. However, certain exemplary embodiments not shownmay include situations wherein pathways are pulled toward the center ofa shield, and remain under the shield evidencing differing electricalcharacteristics, such as inductive behavior, in a balanced or unbalancedstate.

Referring now to FIG. 6, there is shown a stacked multiple circuitincluding embodiment 6900, conductive energy pathways, isolated energysources, isolated energy-utilizing loads, and isolated common conductivepathways. The conductive energy pathways may be conductively coupled toembodiment 6900 by a conductive coupling material, such as, for example,by a solder or industry equivalent. Vias 315, conductive pathwayscontinuing below the surface of the substrate, may couple to theconductive pathways, and may include conductive material that serves asa contiguous conductive pathway for propagating energies. The isolatedcommon conductive pathways may not be directly coupled to the isolatedenergy sources or the isolated energy-utilizing loads. As discussedhereinabove, embodiment 6900 may include four pluralities of pathwaysincluding electrodes and shields, with each plurality electricallyisolated. The shields may be conductively coupled. The conductivelycoupled shields may be externally coupled to an isolated commonconductive pathway, which is not directly conductively coupled to theelectrodes, using a conductive coupling material. As shown in FIG. 6 anelectrode, 815-1, 800-1-IM and 810-1, may be conductively coupled to802GA, 802 GB. A shield, 815-2, 800-2-IM, and 810-2, may be conductivelycoupled to 902GA and 902 GB. These couplings may not be conductivelycoupled to the first plurality of electrodes or the second plurality ofelectrodes. In this configuration, both isolated circuits may beutilizing the isolated and separate voltage references and an isolatedcommon impedance path such as REF 1 and REF 2 in FIG. 6.

Referring now to FIG. 7, there is shown a stacked co-planar multiplecircuit including embodiment 3210, conductive energy pathways, isolatedenergy sources, isolated energy-utilizing loads, and isolated commonconductive pathways. The conductive energy pathways may be conductivelycoupled to embodiment 3210 by a conductive coupling material. Vias 315,conductive pathways continuing below the surface of the substrate, maycouple to the conductive pathways and may include conductive materialthat serves as a contiguous conductive pathway for propagating energies.The isolated common conductive pathways may not be directly coupled tothe isolated energy sources or the isolated energy-utilizing loads. Asdiscussed hereinabove, embodiment 3210 may include four pluralities ofpathways including electrodes and shields, with each pluralityelectrically isolated. The conductively coupled shields may beexternally coupled to an isolated common energy pathway, which is notdirectly conductively coupled to the first or the second plurality ofelectrodes in this co-planar arrangement. A third plurality ofelectrodes, 815-1, 800-1-IM and 810-1 may be conductively coupled to802GA, 802 GB, 815-2 and 800-2-IM, and also, may be conductively coupledto 902GA, 902 GB, and may not be conductively coupled to the firstplurality or the second plurality. In this configuration, both isolatedcircuits may be utilizing a separate and a respective isolated andseparate voltage reference and a separate and a respective isolatedimpedance path, a separate and a respective isolated common impedancepath and at least one separate and respective low inductance pathwaysuch as REF 1 and REF 2 in FIG. 7.

Referring now to FIG. 4A thru to FIG. 7, the termination electrodes890A, 890B, and 891A, 891B, 802GA, 802 GB, and 902GA, 902 GB, may bemonolithic or multi-layered. Termination electrodes 802GA, 802GB, 902GA,902 GB, may be located at other respective portions of a sintered body.Each main body electrode layers 81 or 80, and the associate electrodeextensions 99/79G “X” or 812“X”, may define an electrode which extendsto, and conductively couples to, the associated termination electrodes802GA, 802GB, 902GA, 902GB and 890A, 890B, and 891A, 891B.

The present invention may be utilized for many energy conditioningfunctions that utilize commonly coupled shielding structure element foremulating a center tap of resistor/voltage divider network. Thisresistor/voltage divider network may be normally constructed using aratio of various integrated circuit resistors. However, variousintegrated circuit resistors may be replaced by a device according to anaspect of the present invention, the device utilizing, for example,specific conductive/resistive materials 799A or naturally occurringresistance properties of pathway material 799, or utilizing a variedphysical layout. A voltage dividing function may be present as portionsof a common and shared pathway shield structure are utilized to define acommon voltage reference located at both respective sides of the commonpathway shield structure.

In embodiments, whether initially stacked vertically during amanufacturing process, or in combination with a co-planar pairings asdescribed hereinabove, the number of complementary pathways pairings maybe multiplied in a predetermined manner to create a number of pathwayelement combinations of a generally physically or electrically parallelnature.

Further, although not shown, a device of the present invention may befabricated in silicon and directly incorporated into integrated circuitmicroprocessor circuitry or microprocessor chip packaging. Any suitablemethod for depositing electrically conductive materials may be used,such as plating, sputtering, vapor, electrical, screening, stenciling,vacuum, and chemical including chemical vapor deposition (CVD).

While certain embodiments have been herein described in position as“upper” or “above”, or “lower” or “below”, or any other positional ordirectional description, it will be understood that these descriptionsare merely relative and are not intended to be limiting.

The present invention may be implemented in a number of differentembodiments, including a energy conditioning embodiment as an energyconditioner for an electronic assembly, an energy conditioningsubstrate, an integrated circuit package, an electronic assembly or anelectronic system in the form of a energy conditioning system, and maybe fabricated using various methods. Other embodiments will be readilyapparent to those of ordinary skill in the art.

1. A device, comprising: at least a first and a second plurality ofpathways; wherein said first plurality further comprises at least twopathways arranged electrically isolated from each other and orientatedin a first complementary relationship; wherein at least a first numberof pathways of said second plurality is arranged electrically isolatedfrom a second number of pathways of said second plurality; wherein theat least two pathways of said second plurality are electrically isolatedfrom said first plurality wherein at least two pathways of said firstnumber of pathways of said second plurality are electrically coupled toone another; and wherein at least two pathways of said second number ofpathways of said second plurality are electrically coupled to oneanother.
 2. The device of claim 1, wherein said first number of pathwaysof said second plurality is an odd number greater than one; wherein saidsecond number of pathways of said second plurality is an odd numbergreater than one; wherein at least two pathways of said first number ofpathways of said second plurality are electrically coupled to oneanother; and wherein at least two pathways of said second number ofpathways of said second plurality are electrically coupled to oneanother.
 3. The device of claim 1, further comprising a spacing materialthat at least spaces apart two pathways of said circuit.
 4. The deviceof claim 3, wherein said spacing material comprises a dielectric.
 5. Thedevice of claim 1, wherein said first number of pathways of said secondplurality are in a first alignment; and wherein said second number ofpathways of said second plurality are in a second alignment.
 6. Thedevice of claim 1, wherein said first number of pathways of said secondplurality are in a first superposed alignment; and wherein said secondnumber of pathways of said second plurality are in a second superposedalignment.
 7. The device of claim 5, wherein the first alignment and thesecond alignment are in a superposed alignment.
 8. The device of claim6, wherein the first and the second superposed alignment are in positionat least one on top of the other.
 9. The device of claim 1, wherein atleast two pathways of said first number of pathways are arrangedelectrically coupled to one another in a first alignment; wherein atleast two pathways of said second number of pathways are arrangedelectrically coupled to one another in a second alignment; wherein saidfirst number of pathways is an odd number of pathways greater than one,and wherein said second number of pathways is an odd number of pathwaysgreater than one; and wherein a total number of pathways of said firstplurality is at least an even number greater than two.
 10. The device ofclaim 1, wherein at least two pathways of said first number of pathwaysof said second plurality are arranged in a first superposed alignmentelectrically coupled to 095 one another; wherein at least two pathwaysof said second number of pathways of said second plurality are arrangedin a second superposed alignment electrically coupled to one another;wherein a total number of pathways of second plurality is an odd numbergreater than one; and wherein a total number of pathways of said firstplurality is at least an even number greater than two.
 11. The device ofclaim 9, further comprising a spacing material that at least spacesapart pathways of said circuit arrangement.
 12. The device of claim 10,wherein four pathways of the circuit arrangement are electricallyisolated from one another.
 13. The device of claim 1, wherein said firstplurality of pathways is a plurality of shielded pathways; and whereinsaid second plurality of pathways is a plurality of shielding pathways.14. An electrical arrangement comprising: at least a first and a secondplurality of pathways; wherein the first plurality includes at least onepair of pathways electrically isolated from each other and arranged inmutual complementary position; wherein at least a first number ofpathways of said second plurality is arranged electrically isolated froma second number of pathways of said second plurality, and wherein saidsecond plurality includes at least two pathways electrically isolatedfrom said first 120 plurality; wherein at least two pathways of saidfirst number of pathways of said second plurality are electricallycoupled to one another; wherein at least two pathways of said secondnumber of pathways of said second plurality are electrically coupled toone another; and further comprising a spacing material that at leastspaces apart pathways of said circuit arrangement.
 15. The electricalarrangement of claim 14, wherein at least four pathways of the circuit130 arrangement are electrically isolated from one another.
 16. Theelectrical arrangement of claim 14, wherein at least six pathways of thecircuit arrangement are electrically isolated from one another.
 17. Theelectrical arrangement of claim 14, wherein said second pluralityincludes at least two pathways arranged co-planar to one another; andwherein at least four pathways of the circuit arrangement areelectrically isolated from one another.
 18. The electrical arrangementof claim 14, wherein said second plurality includes at least twopathways arranged co-planar to one another; and wherein at least fourpathways of the circuit arrangement are electrically isolated from oneanother.
 19. The electrical arrangement of claim 14, wherein said firstand said second plurality are arranged in a non co-planar stacking; andwherein four pathways of the circuit arrangement are electricallyisolated from one another.
 20. The electrical arrangement of claim 14,wherein said first plurality of pathways comprises a plurality of vias;and wherein said second plurality of pathways is a plurality ofshielding pathways.
 21. A system, comprising: an integrated circuitpackage having at least one integrated circuit; a plurality of pathwaysconductively coupled together; a first plurality of shields conductivelycoupled together; a second plurality of shields conductively coupledtogether and electrically isolated from at least said first plurality;and wherein each of said shields and said pathways are alternatelyarranged, and wherein said shields develop at least one low impedancepathway suitable for energy propagation away from said integratedcircuit; and wherein said pathways develop a low inductance pathwaysuitable for energy propagation within said integrated circuit package,said energy propagation being conditioned 190 by at least said pluralityof shields.
 22. The system of claim 21, wherein said first and saidsecond pluralities of shields are respectively in a substantiallycoplanar relationship.
 23. The system of claim 21, wherein said firstand said second pluralities of shields are respectively in asubstantially coplanar relationship.
 24. The system of claim 21, whereinone of said first or said second plurality of shields comprises acentering one of said shields, and wherein said first and said secondpluralities of shields and said pathways are arranged in a substantiallybalanced and complementary symmetrical arrangement about said centeringone.
 25. The system of claim 21, wherein one of said first or saidsecond plurality of shields comprises a centering one of said shields,and wherein said first and said second pluralities 205 of shields andsaid pathways are substantially aligned about said centering one. 26.The system of claim 21, wherein each of said first plurality and saidsecond plurality of shields comprises an odd number of shields.
 27. Thedevice of claim 1, in which said device is a first level interconnectarrangement for an integrated circuit.
 28. The device of claim 1, inwhich said device is arranged as a decoupling capacitor.
 29. The deviceof claim 1, in which said device is arranged as a bypass capacitor. 30.The device of claim 1, in which said device is a first levelinterconnect arrangement coupled to an integrated circuit; and whereinat least said first plurality is electrically coupled to said integratedcircuit.
 31. The device of claim 1, in which said device is a firstlevel interconnect arrangement coupled to an integrated circuit; whereinsaid first plurality is electrically coupled to said integrated circuit;and wherein said second plurality is electrically isolated from saidintegrated circuit.
 32. A device comprising: a first electricallyconductive shield layer that resides in a first plane; a thirdelectrically conductive shield layer that resides in a third plane; afifth electrically conductive shield layer that resides in a fifthplane; said third plane is between said first plane and said fifthplane; a first electrically conductive electrode layer that resides in asecond plane, and said second plane is between said first plane and saidthird plane; a third electrically conductive electrode layer thatresides in a fourth plane, said fourth plane is between said third planeand said fifth plane; said device electrically connects said firstelectrically conductive shield layer, said third electrically conductiveshield layer, and said fifth electrically conductive shield layer to oneanother; said first electrically conductive shield layer, said thirdelectrically conductive shield layer, and said fifth electricallyconductive shield layer are stacked, said first electrically conductiveelectrode layer is substantially between said first electricallyconductive shield layer and said third electrically conductive shieldlayer, and said third electrically conductive electrode layer issubstantially between said third electrically conductive shield layerand said fifth electrically conductive shield layer; a secondelectrically conductive shield layer; a fourth electrically conductiveshield layer; a sixth electrically conductive shield layer; a secondelectrically conductive electrode layer; a fourth electricallyconductive electrode layer; said device electrically connects saidsecond electrically conductive shield layer, said fourth electricallyconductive shield layer, and said sixth electrically conductive shieldlayer to one another; said second electrically conductive shield layer,said fourth electrically conductive shield layer, and said sixthelectrically conductive shield layer are stacked, said secondelectrically conductive electrode layer is substantially between saidsecond electrically conductive shield layer said fourth electricallyconductive shield layer, and said fourth electrically conductiveelectrode layer is substantially between said fourth electricallyconductive shield layer and said sixth electrically conductive shieldlayer.
 33. The device of claim 32 wherein: said first electricallyconductive shield layer and said second electrically conductive shieldlayer reside in a first plane; said first electrically conductiveelectrode layer and said second electrically conductive electrode layerreside in a second plane, and said second plane is between said firstplane and said third plane; said third electrically conductive shieldlayer and said fourth electrically conductive shield layer reside in athird plane; said fifth electrically conductive shield layer and saidsixth electrically conductive shield layer reside in a fifth plane; andsaid third electrically conductive electrode layer and said fourthelectrically conductive electrode layer reside in a fourth plane, andsaid fourth plane is between said third plane and said fifth plane. 34.The device of claim 32 wherein: said first electrically conductiveshield layer, said third electrically conductive shield layer and saidfifth electrically conductive shield layer are stacked upon said secondelectrically conductive shield layer, said fourth electricallyconductive shield layer, and said sixth electrically conductive shieldlayer.
 35. The device of claim 34 wherein: said first electricallyconductive electrode layer includes a first electrically conductiveelectrode layer body region and a first electrically conductiveelectrode layer tab region, and said first electrically conductiveelectrode layer tab region protrudes from said first electricallyconductive electrode layer body region in a first direction in saidsecond plane; and said third electrically conductive electrode layerdefines a third electrically conductive electrode layer body region andthird electrically conductive electrode layer tab region, and said thirdelectrically conductive electrode layer tab region protrudes from saidthird electrically conductive electrode layer body region in a seconddirection opposite said first direction.
 36. The device of claim 35wherein: said second electrically conductive electrode layer includes asecond electrically conductive electrode layer body region and a secondelectrically conductive electrode layer tab region, and said secondelectrically conductive electrode layer tab region protrudes from saidsecond electrically conductive electrode layer body region in thirddirection that is perpendicular to said first direction and said seconddirection; and said fourth electrically conductive electrode layerdefines a fourth electrically conductive electrode layer body region andfourth electrically conductive electrode layer tab region, and saidfourth electrically conductive electrode layer tab region protrudes fromsaid fourth electrically conductive electrode layer body region in afourth direction opposite said third direction.
 37. The device of claim32 further comprising additional electrically conductive electrodelayers and additional electrically conductive shield layers.
 38. Thedevice of claim 32 further comprising an electrically conductiveinterconnections between two layers of said device.
 39. The device ofclaim 32 further comprising a sixth electrically conductive shield layeradjacent said first electrically conductive shield layer, and a seventhelectrically conductive shield layer adjacent said fifth electricallyconductive shield layer.
 40. The device of claim 32 further comprising:a set of electrically conductive interconnections; a set of padsprotruding from a surface of said device, and wherein each one of saidset of electrically conductive interconnections connects to a differentone of said set of pads.
 41. The device of claim 40 wherein at leastsome of said set of pads are designed for connection to an integratedcircuit.